對於同步設計,在時序樹上減少時差是很重要的,基於完整繞線中的長度相符的好處, 一個有效的四階段演算法進一步被提出產生具有較小時差的對稱式緩衝時序樹,對於對稱式緩衝時序樹,實驗結果與Shi的方法相比較,我們所提出的方法使用額外2.54%的總連線資源來減少85.78%的時差 It is important for a synchronous design to minimize the clock skew in a clock tree. In this paper, based on the length-matching benefit in exact routing, an efficient four-stage algorithm is further proposed to generate a symmetrical buffered clock tree
