Timing-Constrained I/O Buffer Placement for Flip-Chip Designs

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Title:	Timing-Constrained I/O Buffer Placement for Flip-Chip Designs
Authors:	顏金泰 YAN, JIN-TAI
Contributors:	資訊工程學系 Computer Science & Information Engineering
Keywords:	Flip-chip design;I/O buffer;Timing constraint
Date:	2011
Issue Date:	2014-06-27 01:41:51 (UTC+8)
Abstract:	Due to inappropriate assignment of bump pads or improper placement of I/O buffers, the configured delays of I/O signals may not satisfy the timing requirement inside die core. In this paper, the problem of timing-constrained I/O buffer placement in an are
Appears in Collections:	[Department of Computer Science and Information Engineering] Seminar Papers

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