Routability-Driven Flip-Flop Merging Process for Clock Power Reduction

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Title:	Routability-Driven Flip-Flop Merging Process for Clock Power Reduction
Authors:	顏金泰 YAN, JIN-TAI
Contributors:	資訊工程學系 Computer Science & Information Engineering
Keywords:	Low-power design;Flip-flop merging;Routability
Date:	2010
Issue Date:	2014-06-27 01:40:18 (UTC+8)
Abstract:	The concept of merging some 1-bit flip-flops into a multi-bit flip-flop is applied to reduce dynamic clock power and decrease the total flip-flop area in a synchronous design. To acquire these advantages, the design must be guaranteed to satisfy certain p
Appears in Collections:	[Department of Computer Science and Information Engineering] Seminar Papers

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