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顯示項目526-550 / 744. (共30頁) << < 17 18 19 20 21 22 23 24 25 26 > >> 每頁顯示[10|25|50]項目

日期	題名	作者
2013	Surf-Badge-Based Target Tracking	連振昌; Lien, Cheng-Chang
2011	Synchronization between Wireless UPnP Video and Audio Players	劉懷仁; Liu, Huai-Jen
2008	System-Bus Fault Injection Framework in SystemC Design Platform	陳永源; Chen, Yung-Yuan
2007	System-Level Fault Injection in SystemC Design Platform	陳永源; Chen, Yung-Yuan
2011	Target Coverage in Wireless Sensor Networks	俞征武; Yu, Chang Wu
2011	The Target Coverage Problem in Directional Sensor Networks with Rotatable Angles	梁秋國; Liang, Chiu-Kuo
2005	The target tracking using the spatial-temporal probability model	連振昌; Lien, Cheng-Chang
2013	Techniques for Mitigating the Difference Between Cyber Systems and Physical Systems	俞征武; Yu, Chang Wu
2011	A Texture-Based High Speed Moving Object Detection Method	黃雅軒; huang, yea-shuan
2010	Thermal Via Planning for Temperature Reduction in 3D ICs	顏金泰; YAN, JIN-TAI
2008	Thermal-Driven White Space Redistribution for Block-Level Floorplans	顏金泰; YAN, JIN-TAI
2008	Tidset-based Parallel FP-tree Algorithm for the Frequent Pattern Mining Problem on PC Clusters	游坤明; Yu, K.M.
2004	Timing-Constrained Congestion-Driven Global Routing	顏金泰; YAN, JIN-TAI
2011	Timing-Constrained I/O Buffer Placement for Flip-Chip Designs	顏金泰; YAN, JIN-TAI
2007	Timing-Constrained Redundant Via Insertion for Yield Optimization	顏金泰; YAN, JIN-TAI
2013	Timing-Constrained Replacement Using Spare Cells for Design Changes	顏金泰; YAN, JIN-TAI
2008	Timing-Constrained Yield-driven Redundant Via Insertion	顏金泰; YAN, JIN-TAI
2006	Timing-Constrained Yield-Driven Wire Sizing for Critical Area Minimization	顏金泰; YAN, JIN-TAI
2007	Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization	顏金泰; YAN, JIN-TAI
2008	Timing-Driven Multi-Layer Steiner Tree Construction with Obstacle Avoidance	顏金泰; YAN, JIN-TAI
2006	Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment	顏金泰; YAN, JIN-TAI
2005	Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points	顏金泰; YAN, JIN-TAI
2008	Timing-Driven Steiner Tree Construction for Three-Dimensional ICs	顏金泰; YAN, JIN-TAI
2005	Timing-Driven Steiner Tree Construction with Buffer Insertion	顏金泰; YAN, JIN-TAI
2007	Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance	顏金泰; YAN, JIN-TAI

顯示項目526-550 / 744. (共30頁) << < 17 18 19 20 21 22 23 24 25 26 > >> 每頁顯示[10|25|50]項目