Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter

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Please use this identifier to cite or link to this item: http://chur.chu.edu.tw/handle/987654321/41010

Title:	Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter
Authors:	宋志雲 Sung, Tze-Yun
Contributors:	電子工程學系 Electronics Engineering
Keywords:	Reconfigurable architecture;9/7-5/3 discrete wavelet transform (DWT);horizontal filter (HF)
Date:	2010
Issue Date:	2014-07-18 13:31:02 (UTC+8)
Abstract:	In this paper, the high-efficient and reconfigurable lined-based architectures for the 9/7-5/3 discrete wavelet transform (DWT) based on lifting scheme are proposed. The proposed parallel and pipelined architectures consist of a horizontal filter (HF) and
Appears in Collections:	[Department of Microelectronics] Seminar Papers

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