VLSI Reconfigurable Architecture for 9/7-5/3 Lifting-Based Discrete
Wavelet Transform

CHUR > College of Engineering > Department of Microelectronics > Journal Articles > Item 987654321/37297

Please use this identifier to cite or link to this item: http://chur.chu.edu.tw/handle/987654321/37297

Title:	VLSI Reconfigurable Architecture for 9/7-5/3 Lifting-Based Discrete Wavelet Transform
Authors:	宋志雲 Sung, Tze-Yun
Contributors:	電子工程學系 Electronics Engineering
Keywords:	Reconfigurable architecture;9/7-5/3 discrete wavelet transform;DWT;horizontal filter;HF;vertical
Date:	2009
Issue Date:	2014-07-01 10:20:58 (UTC+8)
Abstract:	Discrete Cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, a novel linear-array of DCT and IDCT is derived from the data flow of subband
Appears in Collections:	[Department of Microelectronics] Journal Articles

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