Utilization of Multi-Bit Flip-Flops for Clock Power Reduction

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題名:	Utilization of Multi-Bit Flip-Flops for Clock Power Reduction
作者:	顏金泰 YAN, JIN-TAI
貢獻者:	資訊工程學系 Computer Science & Information Engineering
關鍵詞:	multi-bit flip-flop;Clocl power
日期:	2012
上傳時間:	2014-06-27 01:43:18 (UTC+8)
摘要:	Utilization of multi-bit flip-flops in a synchronous design has been becoming a significant methodology for clock power reduction. However, some published approaches are usually based on the assumption that the bit number of the flip-flops is continuous o
顯示於類別:	[資訊工程學系] 研討會論文

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