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    "顏金泰"的相關文件 

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    顯示 98 項.

    類別 日期 題名 作者 檔案
    [資訊工程學系] 專題研究計畫 2005 具有訊號完整性的SOC晶片電源供應系統設計 顏金泰
    [資訊工程學系] 專題研究計畫 2006 可避免干擾雜訊的SOC晶片繞線系統的開發 顏金泰
    [資訊工程學系] 專題研究計畫 2007 具有反面晶片技術的晶片與封裝共構繞線發展(I) 顏金泰
    [資訊工程學系] 專題研究計畫 2009 考量溫度限制之三維晶片版面規劃與擺置系統開發 顏金泰
    [資訊工程學系] 專題研究計畫 2010 在高密度印刷電路板設計下的匯流排導向繞線系統開發 顏金泰
    [資訊工程學系] 專題研究計畫 2003 先進製程下的可繞性及效能導向SOC繞線系統的開發(I) 顏金泰
    [資訊工程學系] 專題研究計畫 2011 考量不同佈局需求的單層繞線系統開發 顏金泰
    [資訊工程學系] 研討會論文 2012 Direction-Constrained Layer Assignment for Rectangle Escape Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Resource-Constrained Timing-Driven Link Insertion for Critical Delay Reduction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2011 Simultaneous Escape Routing Based on Routability-Driven Net Ordering 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2011 Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2011 Obstacle-Aware Length-Matching Bus Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Obstacle-Aware Longest Path using Rectangular Pattern Detouring in Routing Grids 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2012 Post-Layout OPE-Predicted Redundant Wire Insertion for Clock Skew Minimization 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Width-constrained Wire Sizing for Non-tree Interconnections 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2012 Top-Down-Based Symmetrical Buffered Clock Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2012 Density-Reduction-Oriented Layer Assignment for Rectangle Escape Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2012 Utilization of Multi-Bit Flip-Flops for Clock Power Reduction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2012 Efficient Assignment of Inter-Die Signals for Die-Stacking SiP Design 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2013 Post-Layout Redundant Wire Insertion for Fixing Min-Delay Violations 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2013 Timing-Constrained Replacement Using Spare Cells for Design Changes 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2013 Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2011 New Optimal Layer Assignment for Bus-Oriented Escape Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2011 Timing-Constrained I/O Buffer Placement for Flip-Chip Designs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2009 Construction of Constrained Multi-Bit Flip-Flops for Clock Power Reduction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Ordered Escape Routing via Routability-Driven Pin Assignment 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2009 Low-Power Multiplier Design with Row and Column Bypassing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Two-Sided Single-Detour Untangling for Bus Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Routability-Driven RDL Routing with Pin Reassignment 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Routability-driven partitioning-based IO assignment for flip-chip designs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Routability-Driven Flip-Flop Merging Process for Clock Power Reduction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Low-Cost Low-Power Bypassing-Based Multiplier Design 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2010 Thermal Via Planning for Temperature Reduction in 3D ICs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2009 Optimal Transformation of Non-tree Topologies for Timing Analysis 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2011 IO Connection Assignment and RDL Routing for Flip-Chip Designs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2012 Resource-Constrained Link Insertion for Delay Reduction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2013 Routability-Constrained Multi-Bit Flip-Flop Construction for Clock Power Reduction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2012 New Optimal Layer Assignment for Bus-Oriented Escape Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2011 Pre-Assignment RDL Routing via Extraction of Maximal Net
    Sequence    		 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2009 Accurate Transformation-Based Timing Analysis for RC Non-tree Circuits 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2009 IO Connection Assignment and RDL Routing for Flip-Chip Designs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2009 RDL Pre-assignment Routing for Flip-Chip Designs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2009 Redundant Wire Insertion for Yield Improvement 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 專書 2009 計算機組織與結構概論 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2008 Simultaneous Assignment of Power Pads and Wires for Reliability-Driven Hierarchical Power Quad-Grids 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2008 Electromigration-aware Rectilinear Steiner Tree Construction for Analog Circuits 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2008 Thermal-Driven White Space Redistribution for Block-Level Floorplans 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2008 Timing-Constrained Yield-driven Redundant Via Insertion 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2008 Flexible Escape Routing for Flip-Chip Designs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2008 Timing-Driven Steiner Tree Construction for Three-Dimensional ICs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2008 Noise-Aware Multiple-Voltage Assignment for gate-Level Power Optimization 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2008 Packing-Driven Sliceable Transformation for 3D Floorplan Designs 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2008 Timing-Driven Multi-Layer Steiner Tree Construction with Obstacle Avoidance 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2008 Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment and Path Reconstruction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2007 Routability-Driven Track Routing for Coupling Capacitance Reduction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2007 Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2007 Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2007 Feasible Assignment of Wire-Bonding Power Pads in Hierarchical Power Quad-Grids for Signal Integrity 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2007 Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity Analysis for Signal Integrity 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2007 Top-Down-Based Timing-Driven Steiner Tree Construction with Wire Sizing and Buffer Insertion 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2007 Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2007 Timing-Constrained Redundant Via Insertion for Yield Optimization 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 Timing-Constrained Yield-Driven Wire Sizing for Critical Area Minimization 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 OPC-Aware Routing Reconstruction for OPE Reduction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 Area-Driven White Space Distribution for Detailed Floorplan Design 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 Floorplan-Aware Decoupling Capacitance Budgeting on Equivalent Circuit Model 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 Multilevel Timing-Constrained Full-Chip Routing in Hierarchical Quad-Grid Model 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 Width and Timing-Constrained Wire Sizing for Critical Area Minimization 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 Optimal Network Analysis in Hierarchical Power Quad-Grids 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 Timing-Driven Octilinear Steiner Tree Construction Based on Steiner-Point Reassignment 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2006 Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2006 Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2006 Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2005 Optimal Shielding Insertion for Inductive Noise Avoidance 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2005 Floorplan-Aware Steiner Tree Reconstruction for Optimal Buffer Insertion 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2005 LB-Packing-Based Floorplan Design on DBL Representation 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2005 Timing-Driven Steiner Tree Construction with Buffer Insertion 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2005 Sliceable Transformation of Non-Slicing Floorplans Based on Vacant Block Insertion in LB-packing Process 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2005 Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2005 Decoupling Capacitance Allocation in Noise-Aware Floorplanning based on DBL Representation 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2005 Wiring Area Optimization in Floorplan-Aware Hierarchical Power Grids 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2005 Timing-Driven Steiner Tree Construction Based on Feasible Assignment of Hidden Steiner Points 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2005 Timing-Constrained Flexibility-Driven Routing Tree Construction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2005 Simultaneous Wiring and Buffer Block Planning for Interconnect-Driven Floorplanning 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2005 Timing-Constrained Construction of Flexibility-Driven Routing Trees 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 期刊論文 2005 Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2004 A Simulated-Annealing-Based Approach for Timing-Constrained Flexibility-Driven Routing Tree Construction 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2004 Double Bound List: A Dynamic Contour-Based Compacted Representation of Non-Slicing Floorplans on LB-Packing Solution Model 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2004 Simultaneous Wiring and Buffer Block Planning with Optimal Wire-Sizing for Interconnect-Driven Floorplanning 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2004 Probabilistic Congestion Prediction in Hierarchical Quad-Grid Model 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2004 Iterative Convergence of Optimal Wire Sizing and Available Buffer Insertion for Zero-Skew Clock Tree Optimization 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2004 Timing-Constrained Congestion-Driven Global Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2003 Congestion-Driven Global Routing Based on Timing-Constrained Routing Flexibilities 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 研討會論文 2003 Optimal Wire Sizing for DME-Based Zero-Skew Clock Routing 顏金泰; YAN, JIN-TAI
    [資訊工程學系] 專題研究計畫 2002 SOC晶片實體整合系統的開發 顏金泰
    [資訊工程學系] 專題研究計畫 2001 在內建區塊佈局上連線導向完全可繞之緩衝器與線段設定規劃 顏金泰
    [資訊工程學系] 專題研究計畫 2000 在深次微米製程上設計有效率之非曼哈坦通道繞線器 顏金泰

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